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W99802G data sheet mobile multimedia processor publication release date: mar. 3, 2006 - 1 - revision a0 table of contents- 1. general des cription ......................................................................................................... 2 2. features ....................................................................................................................... .......... 2 3. pin descri ption................................................................................................................ ..... 7 3.1 W99802G pin de finition ................................................................................................. 7 3.1.1 pin type defi nition .....................................................................................................7 3.1.2 pin li st....................................................................................................................... .7 3.2 W99802G pin assignment (bottom vi ew).................................................................... 15 4. W99802G block diagram................................................................................................... 16 5. electrical chara cteristi cs......................................................................................... 17 5.1 digital absolute maximum ra tings............................................................................... 17 5.2 digital dc charac teristics............................................................................................. 17 5.3 digital ac char acteristics ............................................................................................. 18 5.3.1 reset ac charac teristic s..........................................................................................18 5.3.2 clock input charac teristic s .......................................................................................18 5.3.3 video input ac char acterist ics.................................................................................19 5.3.4 host interface: memory bus ac charac terist ic ........................................................20 5.3.5 lcd interface ac c haracterist ics.............................................................................21 5.3.6 sd/mmc host interface ac characte ristic s .............................................................22 5.3.7 nand flash memory interfac e ac characte ristics ..................................................23 5.3.8 audio i2s interface ac characteri stics .....................................................................24 5.3.9 host universal synchronous serial interface ac char acterist ics .............................25 5.3.10 usb transceiver ac characteri stics........................................................................26 5.4 audio interface (adc) characteri stics.......................................................................... 28 5.4.1 recommend operati on conditi ons........................................................................... 28 5.4.2 electrical char acterist ics ..........................................................................................28 6. package dime nsion ........................................................................................................... 29 7. W99802G applicatio n diagra m ....................................................................................... 30 8. revision history ............................................................................................................... .31
W99802G - 2 - 1. general description W99802G is a highly integrated, low-power and high performance mpeg-4 audio/video chip with embedded memory for multimedia cellular phones. it cont ains a 32-bit arm cpu, sensor isp, jpeg image codec, mpeg-4 video codec, audio engine, 2-d graphics engine, video processing engine, display controller, usb 1.1 device controlle r, and flash memory card interface. W99802G supports 8-bit ycbcr or 10-bit raw data rgb cmos / ccd sensor interface and provides advanced aec / awb / afc algorithm to deliver professional photo image quality. the supported image resolution can be up to 3m pixels. the jpeg image codec is compliant with iso /iec 10918-1 baseline standard and jfif format. it is capable of encoding or decoding 30fps jpeg pictures at vga resolution. the mpeg-4 video codec is compliant with iso/ie c 14496-2 visual standard simple profile level 3. it can also support h.263 short header mode for the im plementation of 3gp movie. the video codec supports smart bit rate control and performs up to 30fps vga simultaneous encode and decode for video conferencing applications. the audio engine integrates a single channel 16-bit adc, as well as audio control interface for external audio codec or melody chip. W99802G c an provide voice recorder and high quality mp3 and aac music playback. the 2-d graphics engine is used for mmi and java acceleration. the video processing engine is used for the image / video data processing. it can provide versatile functions for image / video capture and playback such as sticker, rotation, color effects, etc. the display controller can support dual lcm disp lay and bypass mode. the supported lcm can be up to 262k colors. the usb device controller is compliant with usb1 .1 specification and can support configurable pipes for rich usb functions such as mass storage, pc camera, virtual com port and pictbridge. the flash memory card interface can support embedded nand type flash and sd / mini-sd / mmc / rs-mmc / t-flash for storing multimedia data.t he file system is fat compatible and can be accessed by host through host interface. the internal 32-bit arm cpu handles audio/video sy nchronization, file system and all multimedia functions such as still camera, video camcorder, mp3 player and voice recorder according to the high- level commands from host. the host driver progr ammer can control W99802G without knowing its register programming to shor ten the development cycle. 2. features ? cpu ? built-in 32-bit arm cpu with i-cache and d-cache. ? programmable with cpu operati ng frequency from 200khz to 166mhz. ? program code can be downloaded into program bu ffer through host interface or jtag port. ? integrate jtag port to support real time, non-stop ice function for system development and debug. ? sensor interface and isp ? support up to 3m pixels cmos / ccd image sensor.
W99802G publication release date: mar. 3, 2006 - 3 - revision a0 ? support 8-bit ccir-656 ycbcr or 10-bit raw rgb bayer input format. ? support both master mode and slave mode sensors. ? support universal serial interface to program cmos / ccd image sensor. ? support 30fps real-time preview. ? support sensor isp for color image processing: ? black level clamping ? missing color interpolation ? auto exposure control (aec) ? auto white balance control (awb) ? auto focus control (afc) ? bad pixel concealment ? flash light control ? lens shading compensation ? false color suppression ? edge enhancement ? color correction ? gamma correction ? contrast stretching / hue / saturation adjustment ? support complete software utilities for sensor module calibration. ? video processing engine ? support hardware image sticker function for both preview and compression data. ? support real-time hardware flip / mirror / rotation (90, 180 and 270 degree) function. ? support special image color effect functions su ch as b&w, negative, sepia, oil, emboss, binary, etc. ? support linear scaling down from 1 ~ x/256 with 2d filter for better image quality. ? support yuv-to-rgb and rgb-to-yuv colo r format conversion and data format transformation for video display and image editing. ? mpeg-4 video codec ? support mpeg4 simple profile level 3 comp ression tools and compliant with iso/iec 14496- 2 visual standard. ? support i-vop and p-vop. ? support motion estimation with 16 16 search range and half pixel resolution. ? support ac/dc prediction, 4 motion vector s per macro block, unrestricted motion compensation. ? support rvlc and data partitioning for error resilience. ? support short header mode (h.263 baseline). ? support real-time 30fps video compression/decompression up to vga resolution. ? support smart bit rate control and si multaneous encode/decode for video conferencing application.
W99802G - 4 - ? jpeg image codec ? compliant with iso/iec 10918-1 internal jpeg standard. ? support resolution up to 3m pixels and capabl e of encoding or decoding 30fps real-time vga jpeg. ? support yuv 4:2:2 and 4:2:0 formats encode. ? support yuv 4:4:4, 4:2: 2 and 4:2:0 formats decode. ? support programmable quantization table. ? support programmable huffman table decoding. ? capable of decoding jpeg image with spec ified rectangle to a specified size. ? support resolution scaling up and 1 ~ 8 linear digital zoom. ? support jpeg resizing and trimming. ? support thumbnail image. ? support jpeg exchangeable image file (exif) format. ? audio engine ? support i2s codec interface to connect with external audio codec. ? support audio control interface for external melody chip ? integrate a 16-bit adc for microphone analog input ? support mp3 / amr-wb decoder. ? support aac-lc / amr-nb / adpcm codec. ? 2-d graphics engine ? support 8/16/32-bpp graphics modes. ? support 5 bit block transfer (blt) function with rop function. ? write bitblt ? read bitblt ? copy bitblt ? pattern fill bitblt ? solid fill bitblt ? hardware clipper. ? tile blt. ? mono-to-color expansion for text output acceleration. ? transparency control (sprites). ? image blending (semi-transparency). ? bit plane mask. ? programmable 2d filter functi ons for special color effects. ? support bresenham line and frame drawing. ? display controller ? support 8/12/16/18-bit rgb data output interfac e to connect with 80/68 series mpu type lcm module. ? support lcm resolution up to 240 320. ? support dual lcm control for mpu interfaced lcm.
W99802G publication release date: mar. 3, 2006 - 5 - revision a0 ? support lcm bypass mode that allows the host to access lcm directly while W99802G is in suspend mode. ? support rgb444 (4k colors), rgb565 (65k co lors) and rgb666 (262k colors) color formats for display output. ? support 8/16/32-bit graphics mode osd. ? support graphics / video overlay using color key and alpha blending control. ? support playback pan / tilt / zoom. ? support ccir-656 8-bit yuv output for external tv encoder. ? support picture-in-picture displa y for video conferencing applications. ? usb device controller ? compliant with usb 1.1 specification. ? support four usb pipes including one control pipe and 3 configurable pipes for rich usb functions. ? support usb mass storage. ? support usb pc camera (directshow). ? support usb virtual com port with modem capability. ? support usb pictbridge. ? memory card interface ? support nand type flash. ? support sd, mini-sd, mmc, rs-mmc,and t-flash. ? host bus interface ? support 8/9/16/18-bit parallel slave interface to connect with 80 or 68 series host mpu. ? support bypass mode to allow the host to access the lcm and melody chip directly. ? support dma data transfer between host mpu and W99802G. ? allow host to access W99802G memory buffer and control registers. ? peripheral support ? support two timers and one programmable 24-bit watch-dog timer. ? supports universal synchronous serial interfac e for connecting with synchronous serial device. ? support gpios for system control. ? j2me midp 2.0 graphics / game native layer acceleration ? multimedia file format support ? 3gp (h.263+amr-nb) ? mp4 (mp4+aac-lc) ? avi ? asf ? flash file system support ? support fat12/16/32
W99802G - 6 - ? support long filename. ? power supply ? host interface: 1.8v - 3.3v ? i/o power supply: ? general digital i/o: 2.5v ? 3.3v ? usb transceiver: 3.0v ? 3.3v ? audio adc: 2.5v ? 3.3v ? package: lfbga 184-balls package (10mm x 10mm), lead-free.
W99802G publication release date: mar. 3, 2006 - 7 - revision a0 3. pin description 3.1 W99802G pin definition the following signal types are used in these descriptions. 3.1.1 pin type definition type description i input pin is input pin with schmitt trigger b bi-directional input/output pin bu bi-directional input/output pin with internal pull-up bd bi-directional input/output pin with internal pull-down o output pin a analog input/output pin p power supply pin g ground pin # active low 3.1.2 pin list usb interface pin name pin number type description dp b1 a usb dp (d+) signal dm d2 a usb dm (d-) signal usbvdd d18 p usb power supply +3.3v 0.3v. usbvss e7 g usb ground. sensor or video input interface pin name pin number type description svid[1:0] / gpioa[1:0] j6, n1 bd sensor data input [1:0] gpio function : gpioa[1:0] svid[9:2] k18, l6, g18, r1, j18, n2, p1, k6 id sensor data input [9:2] spclk p2 id clock input from sensor for pixel data svs r2 bd vertical sync. shs n18 bd horizontal sync. sclk l5 o clock output to sensor
W99802G - 8 - sensor or video input interface, continued pin name pin number type description sck / gpioa[2] t1 bu serial interface clock gpio function: gpioa[2] sdi/sda / gpioa[3] l13 bu serial data input/ serial data acknowledge gpio function: gpioa[3] sdo/sde / gpioa[4] l14 bu serial interface data output / serial data enable gpio function: gpioa[4] audio digital interface pin name pin number type description asclk / gpioa[8] f2 bu audio interface: audio system clock gpio function: gpioa[8] ado / gpioa[9] m18 bu audio interface: i2s=> audio data output gpio function: gpioa[9] aws / gpioa[10] f1 bu audio interface: i2s=> audio word select gpio function: gpioa[10] abclk / gpioa[11] g5 bd audio interface: i2s=> audio bit clock output gpio function: gpioa[11] adi / gpioa[12] f8 bd audio interface: i2s=> audio data input gpio function: gpioa[12] arst# / gpioa[13] e1 bd audio interface: audio reset gpio function: gpioa[13] audio analog interface pin name pin number type description cad1 b2 a decoupling for adc mic_in a2 a audio (microphone) input mic_bias b17 a microphone bias vrefc b18 a adc reference voltage ado_avdd a17 p audio adc analog power supply +3.3v ado_avss b15 g audio adc analog ground ado_dvdd j13 p audio digital power supply ado_dvss c1 g audio digital ground
W99802G publication release date: mar. 3, 2006 - 9 - revision a0 jtag interface pins pin name pin number type description tck u12 id jtag test clock tms v16 iu jtag test mode select tdi v12 iu jtag test data in tdo u11 o jtag test data out trst# v11 iu jtag reset uart interface pins pin name pin number type description rts# / gpioa[16] k14 bd request to send / gpio function: gpioa[16] dtr# / gpioa[17] n5 bd data terminal ready gpio function: gpioa[17] sout / gpioa[18] k17 bd serial data output (txd) gpio function: gpioa[18] cts# / gpioa[19] u2 bd clear to send gpio function: gpioa[19] dsr# / gpioa[20] u5 bd data set ready gpio function: gpioa[20] rlsd# / gpioa[21] u4 bd receive line signal detect gpio function: gpioa[21] ri# / gpioa[22] l18 bd ring indicator gpio function: gpioa[22] sin / gpioa[23] m14 bd serial data input (rxd) gpio function: gpioa[23] sout2 / gpioa[24] v2 bd serial data output ?2 (high speed txd) gpio function: gpioa[24] sin2 / gpioa[25] u1 bd serial data input ? 2 (high speed rxd) gpio function: gpioa[25]
W99802G - 10 - lcm interface pin name pin number type description lclk / la0 h13 bd clock input for output data to tv encoder lcm interface (o): address-0, r/s# (cmd/dat#) lclko / lcs0# h5 o clock for digital display data output lcm interface : lcd chip select-0 lcs1# / gpiob[17] g1 bu lcm interface : lcd chip select-1 gpio function : gpiob[17] lwr# / lr/w#/ lhsync h1 o lcm 80-series interface: write enable, active low lcm 68-series interface: ?1? => read, ?0?=> write horizontal sync to tv encoder lrd# / le / lvsync g17 o lcm 80-series interface: read enable, active low lcm 68-series interface: data enable, active high vertical sync to tv encoder ldat [7:0] l1, h17, l2, j17, m1, h6, m2, h18 bu lcm data bus / tv-encoder data bus bit-7_0 ldat [15:8] gpiob[7:0] h2, j5, h14, k5, k1, j2, j14, k2 bu lcm data bus bit-15_8 gpio function : gpiob[7:0] ldat [17:16] / gpiob[9:8] g2,j1 bu lcm data bus bit-17_16 gpio function : gpiob[9:8] lcs2# gpiob[16] g14 bu mcu interface : lcd chip select 2 gpio function : gpiob[16]
W99802G publication release date: mar. 3, 2006 - 11 - revision a0 memory bus interface pin name pin number type description msce# e8 bu memory slave (i) : chip enable signal msa3 b6 bu memory slave (i) : address ? 3 mswr# / msr/w# a5 bu memory slave 80 (i): write enable signal memory slave 68 (i): read/write control msrd# / mse e10 bu memory slave 80 (i): read enable signal memory slave 68 (i): data enable msa[2:0] f17, a4, b14 bd memory slave (i): address msa[2:0] msd[7:0] / f11, b9, f10, a8, e17, a7, e11, b7 bd memory slave (i): data bus bit-7_0 msd[15:8] / gpiob[31:24] f14, a11, b11, a10, d17, b10, e12, a9 bd memory slave (i): data bus bit-15_8 gpio function: gpiob[31:24] msd[16] / gpiob[18] b8 bd memory slave (i): data bus bit-16 gpio function : gpiob[18] msd[17] gpiob[19] a6 bd memory slave (i) : data bus bit-17 gpio function : gpiob[19]
W99802G - 12 - nand / sd / mmc memory card interface pin name pin number type description scs0# / gpios[0] p13 bu nand flash interface =>(o): chip-0 enable gpio function: gpios[0] scs1# / sd_clk / gpios[1] / mmc_clk v14 bu nand flash interface =>(o): chip-1 enable sd : clock gpio function: gpios[1] mmc : clock sale / gpios[2] u18 bu nand flash interface => (o ): address latch enable gpio function: gpios[2] scle / gpios[3] u10 bu nand flash interface => (o): command latch enable gpio function: gpios[3] swe# / gpios[4] p9 bu nand flash interface => (o): write enable gpio function: gpios[4] sre# / gpios[5] u9 bu nand flash interface => (o): read enable gpio function: gpios[5] srb# / gpios[6] t18 bu nand flash interface => (i): ready/busy signal gpio function: gpios[6] swp# / gpios[7] v9 bu nand flash interface => (o): write protect gpio function: gpios[7] sd[0] / sd_dat0 / gpios[8]/ mmc_do n11 bu nand flash interface => (i/o): data bus bit-0 sd : data-0 gpio function: gpios[8] mmc : data-out sd[2:1] / sd_dat[2:1] / gpios[10:9] r17,v8 bu nand flash interface => (i/o): data bus bit-2_1 sd : data-2:1 gpio function: gpios[9] sd[3]/ sd_dat[3] / gpios[11]/ mmc_cs# u8 bu nand flash interface => (i/o): data bus bit-3 sd : data-3 gpio function: gpios[10] mmc : chip select sd[4] sd_cmd / gpios[12]/ mmc_di n10 bu nand (i/o): data bus bit-4 sd : command gpio function: gpios[11] mmc : data-in sd[7:5] / gpios[15:13] u7, n9, v7 bu nand flash interface => (i/o): data bus bit-7_5 gpio function: gpios[15:12]
W99802G publication release date: mar. 3, 2006 - 13 - revision a0 gpio pins pin name pin number type description gpio[0] / hgpio[0] / pclk-a v5 bu general purpose i/o [0] programmable clock output-a (pwm function) gpio[1] / hgpio[1] / msrdyo a12 bu general purpose i/o [1] force gpio[1] to low state. gpio[2] / hgpio[2] / fl_trg p11 bd general purpose i/o [2] flashlight trigger control gpio[3] / hgpio[3] / msinto p18 bd general purpose i/o [3] gpio[5:4] / hgpio[5:4] / feint[1:0] p17, u6 bu general purpose i/o [5:4] fast external interrupt input [1:0] gpio[7:6] / hgpio[7:6] / feint[3:2] r18, v6 bd general purpose i/o [7:6] fast external interrupt input [3:2] gpio[8] e18 bd general purpose i/o [8] gpio[9] e2 bd general purpose i/o [9] gpio[10] d1 bd general purpose i/o [10] gpio[11] f18 bd general purpose i/o [11] gpio[12] usk v3 bu general purpose i/o [12] universal serial interface (usi): usk gpio[13] / udi p7 bu general purpose i/o [13] universal serial interface (usi): udi gpio[14] / udo v4 bu general purpose i/o [14] universal serial interface (usi): udo gpio[15] / ucs0 n8 bu general purpose i/o [15] universal serial interface (usi) : ucs0 gpio[16] / ucs1 p10 bu general purpose i/o [16] universal serial interface (usi) : ucs1 gpio[17] / clk_in2 n17 bu general purpose i/o [17] clock-2 input pin gpio[18] / stdby l17 bd general purpose i/o [18] system standby flag stdby output gpio[19] / pclk-b m17 bd general purpose i/o [19] / programmable clock output-b (pwm function)
W99802G - 14 - miscellaneous pin name pin number type description xin v13 i reference clock input from crystal or clock source. xout u13 o oscillator output to a crys tal. this pin is left unconnected if an external clock source is used. tme u14 id test mode enable. only for test, this pin must be connected to gnd for normal operation. rst# u17 is reset in. this pin is active low to reset chip. s2_pwr a3 o power plate control section 2. power and ground pin name pin number type description vcc f5, f9, m5, n14, p8, b5 p i/o pad buffer power supply (2.5v~3.3v) vcc_lcm c18, e13 p i/o pad buffer to frame buffer power supply (2.6v~3.3v) vcc_hic b12 p host bus interface buffer supply (1.8v~3.3v) gnd f12, f13, f6, f7, g13, g6, k13, m13, m6, n12, n13, n6, n7, v17, b4, a16 g ground. vddhi b13 p internal core logic power supply vddi e9, p12, p6, e6, a15 p internal core logic power supply avddp v15 p pll power supply avssp u15 g pll ground fb_vcc a13, a14 p frame buffer power supply (2.6v ~ 3.3v) vpro v10 id nc
W99802G publication release date: mar. 3, 2006 - 15 - revision a0 3.2 W99802G pin assignment (bottom view) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ? d ado_ avdd gnd vdd1 fb_ vcc fb_ vcc hgpio1 msd14 msd12 msd8 msd4 msd2 msd17 mswr# msa1 s2pwr mic_in d a vre fc mic_ bias ado_ avss msa0 vddhi vcc_ hic msd13 msd10 msd6 msd16 msd0 msa3# vcc gnd cadi dp b vcc_lcm ado_ dvss c usb vdd msd11 dm gpio 10 d gpio8 msd3 d vcc_lcm msd9 msd1 msrd# vddi msce# usb vss cddi d gpi o9 ars t# e gpio 11 msa2 msd15 gnd gnd msd7 msd5 vcc adi gnd gnd vcc asc lk aws f svid7 lrd# lcs2# gnd gnd abc lk ldat 17 lcs 1# g ldat0 ldat6 ldat 13 la0 ldat2 lcs 0# ldat 15 lwr# h svid5 ldat4 ldat9 ado_ dvdd svid1 ldat 14 ldat 10 ldat 16 j svid9 sout rts# gnd svid2 ldat 12 ldat8 ldat 11 k ri# gpio 18 sdo sda svid8 sclk ldat5 ldat7 l ado gpio 19 sin gnd gnd vcc ldat1 ldat3 m shs gpio 17 vcc gnd gnd sd_ dat0 sd_ cmd gpios14 gpio 15 gnd gnd dtr# svid4 svid0 n hgpio3 hgpio5 d fscs0# vddi hgpio 2 gpio 16 gpios4 vcc gpio 13 vddi d spc lk svid3 p hgpio7 sd_ dat2 svs svid6 r gpios6 sck t gpios2 rst# avs sp tme xout tck tdo gpios3 gpios5 sd_ dat3 gpios15 hgpio4 dsr# rlsd# cts# sin2 u d gnd tms avd dp sd_ clk xin tdi trst# vpro gpios7 sd_ dat1 gpios13 hgpio6 hgpio0 gpio 14 gpio 12 sout2 d v
W99802G - 16 - 4. W99802G block diagram i-cache / d-cache mpeg4 codec sensor isp jpeg codec audio i/f lcd ctl. memory card i/f host i/f timer intc uart memory buffer image sensor gpio usb usb audio codec or melody chip host memory card lcds ussi mic adc 2-d g.e. vpe pll & clock control 32-bit risc cpu
W99802G publication release date: mar. 3, 2006 - 17 - revision a0 5. electrical characteristics 5.1 digital absolute maximum ratings table 5-1 absolute maximum ratings parameter min. max. unit ambient temperature -20 85 c storage temperature -40 125 c dc supply voltage for core (1.2v) power (vddi) 0 1.3 v dc supply voltage for i/o (3.3v) power (vddb) 0 3.6 v i/o pin voltage with respect to v ss -0.3 vddb +0.4 v note: exposure to conditions beyond those listed under absolute ma ximum ratings may adversely affect the life and reliability of the device. 5.2 digital dc characteristics table 5-2 dc characteristics symbol parameter conditions min. typ. max. unit vddb power supply for i/o pads 2.6 3.0 3.6 v usbvdd power supply for usb transceiver 3.0 3.30 3.6 v avddp power supply for pll 1.20 1.25 1.30 v vddi power supply for core 1.20 1.25 1.30 v v il input low voltage 0 0.8 v v ih input high voltage 2.0 vddb +0.3 v v ol output low voltage i out = 2ma vss+0.4 v v oh output high voltage i out = -2ma 2.4 v i il input low leakage current v in = 0.4v 10 a i ih input high leakage current v in = 2.4v -10 a i up pull-up current v in = 0v -500 a i pd power down current no load, host inactived. 5 10 a vddb=2.8v 15 ma i dd active current 3gp recording, cif-30fps vddi=1.2v 60 top operation temperature -20 70 c
W99802G - 18 - 5.3 digital ac characteristics 5.3.1 reset ac characteristics rst# t rst figure 5-1 reset timing diagram table 5-3 reset timing symbol parameter conditions min. max. unit t rst reset pulse width 10.0 ms 5.3.2 clock input characteristics xin 1.5 v t high t low xin duty = t high / (t high + t low ) t xin f xin = 1 / t xin figure 5-2 clock input timing diagram table 5-4 clock input timing specification symbol parameter min. typ. max. unit f xin clock input frequency 4 12.0 mhz xin duty clock input duty cycle 45 50 55 % v il (xin) xin input low voltage 0 0.8 v v ih (xin) xin input high voltage 2.0 vddb +0.3 v
W99802G publication release date: mar. 3, 2006 - 19 - revision a0 5.3.3 video input ac characteristics spclk svid[7:0] shs, svs t su t h input valid t high t low t spclk figure 5-3 input video timing diagram table 5-5 input video timing symbol parameter min. max. unit f spclk spclk frequency = 1 / t spclk --- 96 mhz t high spclk clock high time 8.0 --- ns t low spclk clock low time 8.0 --- ns t su svid[9:0], shs, svs setup time 1.0 --- ns t h svid[9:0], shs, svs hold time 1.0 --- ns
W99802G - 20 - 5.3.4 host interface: memory bus ac characteristic fce1_,fce2_ fa2:0] fd[15:0] fiord# valid data t cah t cas t odd t odh t rd fd[15:0] fiowr# valid data t cah t cas t wds t wdh t wr figure 5-4 host interface : memory bus timing diagram table 5-6 host interface: memory bus timing symbol parameter min. max. unit t cas set-up time, fce1_, fce2_ and fa valid before fiord# & fiowr# low 0 --- ns t cah hold time, fce1_, fce2_ and fa valid after fiord# & fiowr# high 0 --- ns t odd fiord# low to data valid delay --- 8.5 ns t odh read data output hold time 2.65 --- ns t rd fiord# pulse width 12 --- ns t wds set-up time, fd valid before fiowr# low 0 --- ns t wdh hold time, fd valid after fiowr# high 0 --- ns t wr fiowr# pulse width 12 --- ns
W99802G publication release date: mar. 3, 2006 - 21 - revision a0 5.3.5 lcd interface ac characteristics lcs_ la0 ldata[15:0] 80 mode : lwr# valid data t lcsh t lcss t ldod t ldoh t lwr t las t lah 68 mode : le t le figure 5-5 lcd interface timing diagram table 5-7 lcd interface timing symbol parameter conditions min. max. unit t lcss chip select set-up time 1/2 --- pclk t lcsh chip select hold time 1/2 --- pclk t las address set-up time 1 --- pclk t lah address hold time 1 --- pclk t ldod write data active delay 0 1/2 pclk t ldoh write data hold time 1/2 --- pclk t lwr lwr# pulse width 80 mode 1/2 --- pclk t le le pulse width 68 mode 1/2 --- pclk
W99802G - 22 - 5.3.6 sd/mmc host interface ac characteristics sd_clk sd : cmd, dat[3:0] mmc : cs, cmd, dat0 t oad output valid sd_clk sd : cmd, dat[3:0] mmc : dat0 t isu t ih input valid t clkh t clkl f sd t oh figure 5-6 sd/mmc host interface timing diagram table 5-8 sd/mmc host interface timing symbol parameter conditions min. max. unit f sd sd/mmc clock frequency identification mode 0 400 khz f sd sd/mmc clock frequency data transfer mode 0 25 mhz t clkh sd/mmc clock high time 10 --- ns t clkl sd/mmc clock low time 10 --- ns t isu cmd & data input setup time 5 --- ns t ih cmd & data input hold time 5 --- ns t oad output active delay (falling edge) --- 14 ns t oh output hold time 20 --- ns
W99802G publication release date: mar. 3, 2006 - 23 - revision a0 5.3.7 nand flash memory interface ac characteristics scs#, sale, scle t wdh t wds t wh t wp t wc swe# sd[7:0] t cacs t cach wad-0 wad-1 wad-2 t rdh t rds t rh t rp sre# sd[7:0] t cacs t cach rd-0 rd-1 rd-2 t rc figure 5-7 nand flash memory interface timing diagram table 5-9 nand flash memory interface timing symbol parameter min. max. unit t cacs scs#, sale, scle setup time before swe#, sre# low 20 --- ns t cach scs#, sale, scle hold time after swe#, sre# high 40 --- ns t wp write pulse width 40 --- ns t wh swe# high time 20 --- ns t wc write cycle time 80 --- ns t wds write data ouptut setup time 30 --- ns t wdh write data output hold time 20 --- ns t rp read pulse width 40 --- ns t rh sre# high time 20 --- ns t rc read cycle time 80 --- ns t rds read data input setup time 30 --- ns t rdh read data input hold time 20 --- ns
W99802G - 24 - 5.3.8 audio i2s interface ac characteristics abclk aws, ado t aos t aoh abclk adi t ais t aih t abclkl t abclk t abclkh figure 5-8 audio i2s in terface timing diagram table 5-10 audio i2s interface timing symbol parameter min. max. unit t abclkh audio bit clock output high time 16 --- ns t abclkh audio bit clock output low time 16 --- ns t abclk audio bit clock output cycle time 40 --- ns t aos audio data output setup time 8 --- ns t aoh audio data output hold time 8 --- ns t ais audio data input setup time 8 --- ns t aih audio data input hold time 8 --- ns
W99802G publication release date: mar. 3, 2006 - 25 - revision a0 5.3.9 host universal synchronous serial interface ac characteristics uck ucs, udo t uos output valid uck udi t iuis t iuih input valid t uck h t uck l t uck t uo h figure 5-9 universal synchronous se rial interface timing diagram table 5-11 host universal synchronous serial interface timing symbol parameter min. max. unit t clkh clock output high time 0.4 --- sclk t clkl clock output low time 0.4 --- sclk t clk clock cycle time 1.0 --- sclk t uos ucs#, udo output setup time 0.3 --- sclk t uoh ucs#, udo output hold time 0.3 --- sclk t uis udi input setup time 0.3 --- sclk t uih udi input hold time 0.3 --- sclk note: sclk = 4 * pclk (apb clock, the frequency of this cl ock is specified by clock divider register-0 & 1)
W99802G - 26 - 5.3.10 usb transceiver ac characteristics low speed: 75ns at c l = 50pf, 300ns at c l = 350pf full speed: 4 to 20ns at c l = 50pf differential data lines 1 0% rise time 90% fall time t f t r 1 0% 90% c l c l figure 5-10 data signal rise and fall time t period differential data lines crossover points paired transitions n * t period + t xjr2 consecutive transitions n * t period + t xjr1 figure 5-11 differential data jitter t period differential data lines crossover point crossover point extended source eop width: t eopt receiver eop width: t eopr1 , t eopr2 diff. data to se0 skew n * t period + t deop figure 5-12 differential to eop transition skew and eop width
W99802G publication release date: mar. 3, 2006 - 27 - revision a0 differential data lines paired transitions n * t period + t jr2 t period consecutive transitions n * t period + t jr1 t jr t jr1 t jr2 figure 5-13 receiver jitter tolerance table 5-12 usb transceiver ac characteristics symbol parameter conditions min. max. unit t r rise time cl = 50 pf 4 20 ns t f fall time cl = 50 pf 4 20 ns t rfm rise/fall time matching 90 110 % t drate full speed data rate average bit rate (12 mb/s 0.25%) 11.97 12.03 mbps t dj1 t dj2 source differential driver jitter to next transition for paired transitions -3.5 -4.0 3.5 4.0 ns ns t eopt source eop width 160 175 ns t deop differential to eop transition skew -2 5 ns t jr1 t jr2 receiver data jitter tolerance to next transition for paired transitions -18.5 -9 18.5 9 ns ns t eopr1 t eopr2 eop width at receiver must reject as eop must accept as eop 40 82 ns ns
W99802G - 28 - 5.4 audio interface (adc) characteristics 5.4.1 recommend operation conditions parameter symbol min. typ. max. unit digital supply range ado_dvdd 1.1 1.2 1.3 v analog supply range avdd 2.5 3.0 3.6 v ground dvss, avss 0 v temperature ta -20 85 o c 5.4.2 electrical characteristics conditions: dvdd = 1.2v, avdd = 2.7v, ta = 30 o c, 1khz signal, fs = 48 khz, 16-bit audio data. parameter sym. test condition min. typ. max. unit adc : analog input (mic_in) full scale input signal level (for adc 0db input at 0db gain) v infs avdd = 2.5v 0.707 v rms input resistance 11.2 44.8 kohm. input capacitance 10 pf signal to noise ratio snr 70 db dynamic range 90 95 db total harmonic distortion thd 70 db analog reference level reference voltage vrefc -3% 1.2 +3% v microphone bias bias voltage v micbias 3ma load current -5% 0.9* avdd +5% v bias current source i micbias 3 ma
W99802G publication release date: mar. 3, 2006 - 29 - revision a0 6. package dimension W99802G package outline (184l stk lfbga) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l m n p r t u v 0.5 8.50 10.00 + 0.15 8.50 0.5 10.00 + 0.15 bottom view a1 corner a b c d e f g h j k l m n p r t u v 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 a1 corner top view c 0.26ref. 0.86ref. 0.20 c seating plane a 0.16 ~ 0.26 1.60 max. 0.08 c b 0.15(4x) 0.27~0.37(184x) package size : 10.00x10.00x1.60mm unit : mm ball pitch : 0.50 ball diameter : 0.3 substrate thickness : 0.26 mold thickness : 0.86 package type : 184l stk lfbga 0.08 m c 0.15 m c a b W99802G
W99802G - 30 - 7. W99802G application diagram mpeg4 audio jpeg fmi sensor dsp hic 2d ge vpe arm cpu vpost vc e apb usb high speed uart ussi gpio pwm nand sensor module memory buffe r base band lcm1 lcm2 melody mi c
W99802G publication release date: mar. 3, 2006 - 31 - revision a0 8. revision history version date page description a0 mar. 3, 2006 public edition important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgi cal implantation, atomic energy control instruments, airplane or spaceship instrument s, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. further more, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. use of this product W99802G in any manne r that complies with any of the mp3, wma, mpeg4, 3gp, aac, and/or any other technology standards is expressly prohibited without a license under appl icable patents in each of the mp3, wma, mpeg4, 3gp, aac, and/or any other technology standards patent portfolio, which license is avaibl e from respective competent authority licensor.? ?neither shall winbond be liable for any license fee, royalty, and/or any other expense or cost accrued from the said license(s), nor shall winbond be responsible for infringement of th e right of patent caused out of the inappropriate use of this product by customer. headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5665577 http://www.winbond.com.tw/ taipei office tel: 886-2-8177-7168 fax: 886-2-8751-3579 winbond electronics corporation america 2727 north first street, san jose, ca 95134, u.s.a. tel: 1-408-9436666 fax: 1-408-5441798 winbond electronics (h.k.) ltd. no. 378 kwun tong rd., kowloon, hong kong fax: 852-27552064 unit 9-15, 22f, millennium city, tel: 852-27513100 please note that all data and specifications are subject to change without notice. all the trade marks of products and companies mentioned in this data sheet belong to their respective owners. winbond electronics (shanghai) ltd. 200336 china fax: 86-21-62365998 27f, 2299 yan an w. rd. shanghai, tel: 86-21-62365999 winbond electronics corporation japan shinyokohama kohoku-ku, yokohama, 222-0033 fax: 81-45-4781800 7f daini-ueno bldg, 3-7-18 tel: 81-45-4781881 9f, no.480, rueiguang rd., neihu district, taipei, 114, taiwan, r.o.c.

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